The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a capacitor.
In recent years, as memory devices are highly integrated, shrink in size and operate at high speed, an occupation area of a capacitor is decreasing in the memory device. Notwithstanding, the capacitor for driving a semiconductor device still requires a capacitance equal to or higher than ever. To secure high capacitance, therefore, there has been announced a method in which a storage node (SN) oxide layer is thickly formed and the SN oxide layer is then dry-etched to increase a height of a capacitor region. However, as the SN oxide layer is thickly formed, a critical dimension (CD) of the bottom of the capacitor region is reduced due to characteristics of the dry etching process itself, thus leading to the deterioration of electrical properties of the device, for instance, the deterioration of capacitance.
To improve the critical dimension of the bottom of the capacitor region, there has been proposed another method in which a bilayered SN oxide layer having thin films with different wet etch rates is employed to increase the critical dimension of the bottom of the capacitor region.
In detail, an interlayer dielectric (ILD) layer is formed over a substrate where a semiconductor circuit including transistors, bit lines, etc., is formed, and thereafter the ILD layer is etched to form a storage node contact hole exposing a portion of a substrate. After a polysilicon layer is deposited on the ILD layer to fill the storage contact hole, the polysilicon layer is planarized through a chemical mechanical polishing (CMP) process until a surface of the ILD layer is exposed, thereby forming a polysilicon plug filling the storage node contact hole. Herein, the polysilicon plug is called a storage node contact plug.
Afterwards, a nitride layer and an SN oxide layer are sequentially formed on the ILD layer including the storage node contact plug. The nitride layer serves as an etch stop layer and the SN oxide layer determines a height of the storage node. The SN oxide layer has a bilayered structure in which two oxide layers having different wet etch rates are stacked over the nitride layer. Hereinafter, a lower layer of the bilayered SN oxide layer is referred to as a first SN oxide layer, and an upper layer of the bilayered SN oxide layer is referred to as a second SN oxide layer. The first SN oxide layer includes a material having a higher wet etch rate than the second SN oxide layer. The first SN oxide layer includes a phospho-silicate glass (PSG) layer or a boro-phospho-silicate glass (BPSG) layer. The second SN oxide layer includes a material having a low wet etch rate such as a plasma enhanced tetra ethyl ortho silicate (PETEOS) layer.
A mask pattern is formed over the second SN oxide layer for defining a capacitor region, and the first and the second SN oxide layers are dry-etched using the mask pattern as an etch barrier to form a capacitor region, which is referred to as a first capacitor region. Since the bilayered SN oxide layer is very high, the width of the first capacitor region gradually decreases toward the bottom. Thereafter, a wet etch process is performed to enlarge the bottom width of the first capacitor region, thereby forming a final capacitor region, i.e., a second capacitor region, with the enlarged bottom width. If the first and the second SN oxide layers having different wet etch rates are wet-etched, the wet etching is performed faster on the first SN oxide layer than the second SN oxide layer because the first SN oxide layer has a higher wet etch rate than the second SN oxide layer. Resultingly, it is possible to enlarge the width of the bottom of the capacitor region.
However, the above-described method has a limitation as follows. The PSG layer or the BPSG layer for the first SN oxide layer is deposited using chemical vapor deposition (CVD), and thus a concentration of the SN oxide layer is determined depending on a concentration of phosphorous (P) or boron (B). Here, a wet etch rate of the PSG layer or the BPSG layer increases as an impurity concentration in the PSG layer or the BPSG layer increases. However, if the PSG or the BPSG is deposited using the CVD, the impurity concentration of the layer is not uniform on the whole, thus causing a high-concentration part of the SN oxide layer to be over-etched during the wet etching process. Accordingly, if the first SN oxide layer is over-etched, a bridge phenomenon may occur between capacitor electrodes in the case where material for a capacitor electrode is deposited onto the capacitor region, leading to the decrease in device reliability and semiconductor yield.
FIG. 1 is a micrographic view of a bridge phenomenon between typical capacitors. Referring to FIG. 1, it can be observed that the bridge occurs between capacitor electrodes after wet etch process, particularly under the capacitor electrode. The reason is that a concentration of a lower layer formed of the PSG layer or the BPSG layer in a bilayered SN oxide layer is not uniform, and thus the high-concentration part is over-etched during the wet etch process.